1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to an integrated circuit adapted for ECO and FIB debug.
2. Description of Related Art
During the development of electronic circuits, designers usually perform continuous tests, debugs and revision (including adding/removing devices and cutting/connecting conductive wires) for samples designed thereby. During development of printed circuit boards (PCB), designers can easily and properly modify the circuits (including adding devices or cutting/connecting conductive wires). Compared with PCB, devices cannot be added into integrated circuits after the fabrication thereof are complete. Therefore, integrated circuit designers put spare cells or spare gates in pre-determined area of the integrated circuit layouts for Engineering Change Order (ECO) revision. The spare cell has preset electrical function or logic function. The input terminal and the output terminal of the spare cell do not contact with other cells for the purpose of circuit debug/revision.
A prior art related to this field is U.S. Pat. No. 6,404,226 B1. FIG. 1A is a drawing showing a prior art spare cell of an integrated circuit. As shown in FIG. 1A, the surface of the substrate 110 comprises cells 120, 130 and 140. The cells 130 and 140 are standard cells; the cell 120 is a spare cell. A first metal layer, a second metal layer, a third metal layer and a fourth metal layer are formed over the substrate 110, wherein it is assumed that the fourth metal layer is the top metal layer. M1, M2, M3 and M4 represent the terminal pads or wires of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer. The metal layers are electrically connected by vias, such as via 150 shown in this figure. The structure electrically connecting the metal layers by vias is called a via structure. The signal to be processed, for example, goes into the input terminal of the spare cell 130 through the via structure from the conductive wire 101 of the first metal layer. After the signal is processed by the cell 130, the signal goes to the fourth metal layer, i.e. the top metal layer, from the output terminal of the cell through the via structure. Then the signal goes to the input terminal of next circuit, such as the cell 140, through the via structure. At this moment, the spare cell 120 is not used.
When ECO is performed for replacing the spare cell 120 for the cell 130, a plurality of photo masks should be revised for generating the circuit shown in FIG. 1B. FIG. 1B is a drawing showing a connection structure with the replacement by a spare cell. The via 150 is removed for cutting the electrical connection between the cells 130 and 140. In addition, the via 155 is added and the conductive wire 156 extends coupling the via 155. In the third metal layer, a conductive wire 152 is added between the terminal pad 151 and 153 so that the signal to be processed goes to the input terminal of the spare cell 120 from the conductive wire 101 through the via structure. After the signal is processed by the spare cell 120, the signal goes to the conductive wire 156 of the fourth metal layer from the output terminal of the cell through the via structure. Then the signal goes to the input terminal of next circuit, such as the cell 140, through the via structure.
Accordingly, the prior art ECO should revise a plurality of photo masks. The design cost is thus increased. When Fiber Ion Beam (FIB) debug is performed, the signal should be transferred to the top layer. Therefore, a plurality of masks should be revised in accordance with the prior art technology. The layout design of the prior art spare cell is not convenient to perform FIB debug and therefore expensive.